Building Semiconductor Chips In India Is No Longer The Hard Part — It Is Building The Ecosystem Around Them

Design, fabrication, and packaging of semiconductor chips now exist on Indian soil. The hard part is connecting them — getting Indian fabs to serve Indian designers, Indian packagers to price for Indian volumes, and Indian OEMs to specify Indian chips.

The chip Pratap Narayan Singh, co-founder and Chief Technology Officer of Vervesemi Microelectronics, picks up off his desk in Greater Noida is roughly the size of a fingernail and weighs less than a grain of rice. "This one is for weighing scales," he says, dropping it back down. "India needs about five billion of these a year, it can be used in multiple devices. Today, every one of them comes from outside." His co-founder and Chief Executive Officer of Vervesemi, Rakesh Malik leans across the table, pointing to a bigger chip they have made for ISRO, and adds, deadpan: "If you took the weight of this chip and the same weight of gold, the chip would be more expensive than gold." The two chips sit at opposite ends of the market. The high-volume chip, sold in billions, must compete on price with global incumbents, and this is precisely the market India is finding hard to crack. The ISRO chip, made in small numbers with no real competitor, commands a premium. Malik draws a flowchart on a sheet of paper. A box marked DESIGN, with 'six months' written underneath. An arrow to a box marked FAB, 'three months.' An arrow to TEST AND DESIGN CHANGES, three months. To MASK AND FULL PRODUCTION FAB, three months. To VOLUME TEST, three months. To PACKAGING. Back to the customer. He totals it: roughly two years. "All of that," he tells Swarajya, tapping the page, "happens outside India today. The first box is in this office. The last box is in this office. Everything in between is somewhere else."

Left: Vervesemi's chip for weighing scale, strain gauge. Right: Chip for ISRO. (PC: Diksha Yadav/Swarajya)

The production cycle of a chip designed by Vervesemi Microelectronics in Greater Noida. Of the seven stages, only the first and the last happen in India. The full round trip takes roughly two years.

Vervesemi's testing lab. (PC: Diksha Yadav/Swarajya)

A two-year journey that leaves India after the first office Vervesemi Microelectronics, the company Singh and Malik founded, is one of 24 firms sanctioned under India's Design Linked Incentive (DLI) scheme. It operates out of the Greater Noida special economic zone. "After working with ST Microelectronics since 1991," Malik says, "we started this venture in 2017 with the goal of doing something meaningful, and doing it in India. When we started, only two or three Indian fabless companies existed. Some of those were later acquired by bigger players." The company today holds more than 110 intellectual property cores and 25 chip families, and ships into customers across Europe, Japan and the United States. But the production journey reveals the gap. A chip designed in its Greater Noida office travels to a Taiwanese or Korean foundry to be manufactured. The finished wafer then goes to another country for packaging. The packaged chip returns to India to be sold to an Indian customer, or ships onward directly to a customer abroad. Vervesemi's story is the Indian fabless story in miniature: the design brain sits in Greater Noida while the body that should surround it — fabrication, packaging, the supply chain — sits abroad. Why design ownership matters more than import substitution To see why the gap matters, one has to understand where the value sits in a semiconductor product. Chip design captures up to 50 per cent of the total value addition in a finished semiconductor. The chip itself can account for 20 to 50 per cent of a device's bill of materials. Globally, fabless companies, that is, firms that design chips but do not manufacture them, drive roughly 30 to 35 per cent of all semiconductor sales. The strategic logic of building indigenous design capability, therefore, has little to do with import substitution. It is about owning the intellectual property that determines what the chip does, which market it serves, and who controls its evolution. Design ownership is what separates principals from contractors in the semiconductor economy. India already has the talent base for the higher-value layer. Roughly 20 per cent of the world's chip-design engineers are Indian. The unfinished work is making sure that capability translates into a real Indian semiconductor industry, rather than into a global one staffed by Indians. Three layers built, one connecting tissue missing India has built three semiconductor layers in less than four years. The first is the fabless layer: the 24 DLI companies, plus more than 50 global capability centres of multinationals doing chip design from Indian offices. The second is the packaging layer: three commercially operational outsourced assembly and test (OSAT) units in Gujarat, with another four under construction. The third is the fab layer, the actual manufacturing factory. Tata Electronics' Dholera plant is expected to produce first silicon by December 2026 and reach full production by 2028. The architecture is in place; the tissue connecting its three layers is missing. The fabs are being built, but there are no discussions yet on whether the specifications will serve Indian fabless companies at competitive prices. The packaging houses are taking foreign orders; they are not yet ready to supply Indian fabless companies at competitive prices. The fabless cohort continues to route most of its production to foreign foundries because that is where its chips have always been made. The gap is solvable, but the window in which it must be solved is narrow.

India built three layers of a semiconductor industry in four years. The arrows that should connect them are still missing.

Consider one example. India installs about 50 million smart electricity meters every year. Each one contains a microcontroller and a power-measurement chip. Every single one of those chips today is imported. Vervesemi has an Indian alternative. Its smart metering chip is qualified and in advanced testing, and the company has presented it to the Union Power Ministry, where the meeting went well. The chip is ready, the volume is enormous, and the one thing missing is the mechanism by which the Indian chip reaches the Indian smart meter. Every claim about an Indian semiconductor ecosystem is, until that mechanism is built, a claim about the architecture rather than the outcome.

Fifty million smart meters a year. A qualified Indian chip sitting ready. No road between them — that is what an ecosystem gap looks like in practice.

Left: Vervesemi's MCU for Motor Control under DLI. Right: Smart Metering IC. (PC: Diksha Yadav/Swarajya)

A look at precision engineering: A discarded silicon wafer featuring high-performance weighing scale chips by Vervesemi. (PC: Diksha Yadav/Swarajya)

How a chip actually gets made The semiconductor industry has three core roles. A fabless company designs the chip. A foundry, or fab, fabricates the design onto silicon wafers using extraordinarily complex photolithography. An OSAT company cuts the finished wafer into individual chips, packages them in plastic or ceramic housings, tests them, and ships them to customers. This division of labour emerged in the 1980s, when Taiwan Semiconductor Manufacturing Company (TSMC) introduced the pure-play foundry: a factory that fabricated chips for other companies but did not design or sell any of its own. The model unlocked the fabless revolution. NVIDIA, Qualcomm, Broadcom, AMD, MediaTek and dozens of others could now design chips without owning factories. Today, all the most valuable chip companies in the world are fabless, including the world's most valuable company by market capitalisation. The fab itself, the actual factory, is increasingly the geopolitical asset, with TSMC's Taiwan plants and Samsung's Korean plants producing the chips that everyone else designs. This is the world India is trying to enter, at all three layers, in parallel. What ISM 1.0 built India entered this game in late 2021 with the announcement of the India Semiconductor Mission (ISM). The first phase committed roughly Rs 76,000 crore in incentives, structured across three streams. The first stream, fabrication, invited applications from companies willing to set up wafer fabs in India, with the centre and state governments together offering up to 75 per cent capital subsidy. Tata Electronics' partnership with Taiwan's PSMC for the 28-to-110-nanometre Dholera fab emerged from this round, alongside a compound semiconductor fab in Sanand. The second stream, OSAT and assembly-test-mark-packaging (ATMP), built the back-end of the supply chain. Three units are now commercially operational: Micron's Sanand memory ATMP, CG Semi's joint venture with Renesas and Stars Microelectronics, and Kaynes Semicon's Sanand unit, inaugurated by the prime minister on 31 March 2026. Tata's OSAT facility at Jagiroad in Assam, targeting 48 million chips per day for automotive and EV applications, HCL-Foxconn's Jewar facility in Uttar Pradesh, and the Suchi Semicon unit in Surat are all under construction. The August 2025 round of approvals broadened the architecture further. SiCSem in Bhubaneswar is developing India's first commercial silicon-carbide fab, a process used in power electronics for electric vehicles and grid infrastructure. 3D Glass Solutions in Odisha is setting up advanced glass-substrate packaging for 5G and 6G radio frequency applications. CDIL's expansion at Mohali adds high-power discrete semiconductor capacity. And Lam Research, the American semiconductor equipment company, committed over $1 billion to a manufacturing and engineering centre in Karnataka, the first major global tool supplier to invest at this scale in India outside the fabs themselves. The Lam commitment matters disproportionately to the size of the cheque. Semiconductor equipment is the deepest moat in the industry. The Dutch firm ASML's near-monopoly on extreme-ultraviolet lithography is the canonical example. The upstream layer of the ecosystem, the machines that make the chips, is for the first time beginning to develop alongside the fab and OSAT layers in India. How the design ecosystem was seeded The third stream, and the one with which this article is most concerned, was the design ecosystem. The Design Linked Incentive (DLI) scheme funded chip-design startups directly through two components. The Product Design Linked Incentive reimburses up to 50 per cent of eligible design expenditure, that is, manpower, electronic design automation (EDA) software licences, intellectual property registration and prototype validation, capped at Rs 15 crore per project. The Deployment Linked Incentive rewards commercialisation at 4 to 6 per cent of net sales over five years, capped at Rs 30 crore per applicant. Alongside the grants, the scheme stood up the ChipIN Centre at the Centre for Development of Advanced Computing (C-DAC) in Bengaluru. The centre provides DLI-supported companies and academic institutions with access to industry-grade EDA tools from Cadence, Synopsys and Siemens. These are software packages whose individual licences cost crores per year, and which had previously been accessible only inside the R&D arms of multinationals. The shift in baseline has been dramatic. Nishit Gupta, Scientist E at the Ministry of Electronics and Information Technology (MeitY) closely involved with the DLI scheme, puts it sharply. "In 75 years since independence, India might not have received Rs 150-200 crore of VC funding in the chip design space. I'm talking about companies designing chips for developing their own products, not services. In 75 years, that was the total. In the last three years, we have 22-24 DLI companies, and each of them has raised Rs 100 to 150 crore," he tells Swarajya. By January 2026, the supported cohort had completed 16 tape-outs (the final design hand-off to the foundry), fabricated six chips, filed 10 patents, and developed more than 140 reusable IP cores. The shared EDA grid had recorded over 54 lakh hours of cumulative usage and supported roughly 95 startups, with around one lakh engineers and students across 400 organisations using the licensed tools. C-DAC describes it as the largest shared EDA infrastructure of its kind in the world. More than 1,000 specialised engineers have been trained through DLI-supported projects. India also inaugurated its first 3-nanometre design centres in Noida and Bengaluru in 2025. The cohort, in its diversity Within this cohort sits a strikingly diverse set of companies. Each is working on a different technology node and a different application class. Mindgrove Technologies, incubated at IIT Madras, has launched India's first commercial RISC-V system-on-chip, the Secure IoT S2401, fabricated at 28 nanometre. InCore Semiconductors is making a series of microprocessors as licensable intellectual property; their cores will sit inside other people's chips. NetraSemi is making automotive and surveillance image sensors. C2I Semiconductors is redesigning grid-to-chip electricity supply, and has raised Rs 170 crore in venture funding. Fermionic Design is making a radio-frequency beamforming chip for satellite signal reception. The company is working to supply its chips to Indian defence and space establishments, including Bharat Electronics Limited. AAGYAVISION is making a drone-detection chip, a sentiment-driven approval in the post-Operation Sindoor environment. BigEndian Semiconductors is making a CCTV chip, holding Rs 15 crore in DLI funding and a $6 million venture round (roughly $9 million in total). Companies are also looking for funding under the Department of Science and Technology's Research, Development and Innovation (RDI) scheme, what Gupta calls "the graduate school graduating into the post-graduate phase." Aheesa Digital Innovations is making a Wi-Fi router chip. They designed Vihaan-I, India's first indigenous RISC-V-based broadband access system-on-chip (SoC) for fibre broadband Optical Network Terminal devices. Every Indian broadband router today contains a foreign chip; Aheesa is the only Indian alternative under development right now. Each of these companies has its own product, its own customer base, its own technology node, and its own process requirement. The diversity is both the point and the problem. What a 'node' really is, and why it complicates alignment Tata Dholera, the first commercial silicon fab in India, will run at five nodes: 110, 90, 55, 40 and 28 nanometre. At Semi-Conductor Laboratory in Mohali, India has had 180-nanometre capability for decades. On paper, the range looks comprehensive. "From 28 to 180 nanometre is exactly the band where roughly 70 per cent of the global wafer market lives," Amitesh Sinha, the Additional Secretary at MeitY and the CEO of the India Semiconductor Mission tells Swarajya. Sinha is direct about the strategic logic. The applications in this range are precisely the ones where Indian original equipment manufacturers (OEMs) exist as potential customers. Maruti, Tata Motors and Mahindra in automobiles. Reliance Jio, Vodafone Idea and BSNL in telecommunications. A long tail of industrial and power-electronics OEMs. "End-to-end solution is possible," Sinha says of these segments. "OEMs are sitting here, fabs of matching nodes will be here, packaging of matching nodes is there." The strategy is to capture the legacy-node belt that anchors most of the global market by chip count. To see what is missing, one has to understand that the same node number at two different fabs does not mean the same fab. A 'node' is shorthand for a generation of manufacturing technology, but each fab tunes that technology to its own machines and process recipes. Tata Dholera's 28-nanometre line will use machines bought new from suppliers, calibrated to PSMC's process recipes, while PSMC in Taiwan uses older equipment honed across two decades of production. The new fab will need its own alignment period. When STMicroelectronics and TSMC aligned their 28-nanometre processes some years ago, the work took two to three years of machine-by-machine tuning. Dr Mukul Sarkar, a professor at IIT Delhi and the founder of Orvis Semi, one of the 24 DLI companies, puts the technical reality plainly. "Process flows for every application are different. You cannot do everything in 180 nanometre." The masks, the costs, and the moulds To see how this becomes a commercial problem, one has to understand how a chip actually moves from design to wafer. A fabless company can do this in two ways. It can take its design to a multi-project wafer (MPW) run, a shared fabrication slot in which multiple companies' designs are placed on the same wafer to amortise the cost of the photolithographic masks. Or it can commission a full-mask run, in which a complete set of masks is created for that one design alone. The masks, a set of patterned plates that define every layer of every transistor on the wafer, are the most expensive single input to chip production. A 28-nanometre full-mask set costs in the region of $2 million. At 7 nanometre, it is closer to $10 million. At 2 nanometre, eight figures. The mask is the mould. Once made, it lives inside the foundry's cleanroom and can stamp out wafers, usually hundreds at a time, for the life of the production run, which is fifteen years or so. The mask is a recipe for one specific fab's machines, calibrated to one specific process flow. This is where India's plan meets its first piece of engineering reality. Sinha argues, optimistically, that fabless companies can switch nodes within a band: if you were targeting 65 nanometre, you can target 55 or 50 instead. The shift involves redesign but is not prohibitive. Industry voices add that since the fab will need its own alignment period of at least two years, which can happen in parallel with fabless firms designing the chip, if this alignment between Indian fabless and Indian fab is to happen at all, the right time to begin is now. Tata Dholera's first line is a power-management node, optimised for chips that switch high currents and voltages efficiently, the kind of chips that go inside motors, batteries and chargers. It is not the same 180-nanometre line that an image sensor company would use, even though both might be described as '180 nanometre.' By Sarkar's count, of the roughly 40 chip-design projects funded under DLI, around three or four are working on power management. Most are doing analogue, mixed-signal, radio frequency, processors and specialty chips. Tata's first line, in its first phase, cannot serve most of them. Tata will, over time, add more process variants. But each variant requires its own stabilisation, its own intellectual property ecosystem, its own qualified library of standard cells and memory blocks. A fab is a set of recipes, each one tuned to a class of chips, each one demanding its own ecosystem around it. The IP ecosystem that has to be built around a fab That ecosystem is the second piece of engineering reality. A modern chip is a composition of intellectual property (IP) blocks. For example, for an audio device: The processor at its heart is one block, licensed from a company like Arm or InCore or designed in-house. The analogue-to-digital converter is another block. The digital signal processor is another. The memory controller is another. The input-output interfaces (USB, SPI, UART, CAN) are each their own blocks. The libraries of standard cells, the basic building units like flip-flops and logic gates, are another. The memory itself, embedded SRAM or flash, is licensed from yet another specialised company. "A fab does not just need machines; it needs alliance partners for each of these layers, each of them developing and qualifying their intellectual property on that specific fab's process," Malik of Vervesemi tells Swarajya. TSMC has hundreds of such alliance partners around its leading nodes, and PSMC has its own ecosystem around its Taiwan fab. Tata Dholera has none of this yet, and has to start building it now, before the fab is ready for operation. "There is no partner of analogue IP for Tata," Malik says. "There is no partner."

No announcement by Tata of any alliance build-up in India has happened yet. But if the plan is to build the fab ecosystem with Indian design companies, such an announcement has to happen now, because design firms will then start building their new chips in alignment with the Tata fab and vice versa, which is a time-consuming process. Additionally, for Indian fabless and Indian fab to align in time, ISM 2.0 will need to provide design-specific incentives to attract fabless companies onto Tata's lines. Unless fabrication at Tata's facility is price competitive (significantly less than the foreign fabs), they will not take the risk of shifting to a new fab. The ecosystem will not assemble by gravity. It has to be pulled.

A single audio device chip requires six or more categories of IP alliance partners, each developing and qualifying their intellectual property on the fab's specific process. TSMC has hundreds of such partners. Tata Dholera, at present, has none.

The cost gap is not 10-15%. It is multiples.

The cost arithmetic that defeats the 'Indian fab will be cheaper' theory One approach being discussed is that Indian fabless companies could align themselves with Taiwan's PSMC and then shift to Dholera once Tata's fab is ready. This is theoretically clean, but it runs into two practical problems. The first is that the company would still need to go through the complete machine-by-machine tuning process for their chips once they shift, as mentioned earlier. The second, and more crucial, is the cost arithmetic. When Vervesemi began to think of the alignment process with PSMC, assuming that by working with PSMC's Taiwan line first they could later port the same design to Dholera, the company asked for a price quote. PSMC's price was roughly 20 per cent above what Vervesemi already gets from the Taiwan and Korean fabs it uses. The 'Indian fab will solve the cost problem' theory failed at the first price negotiation. Two reasons. First, PSMC's Taiwan line, while the technology partner for Dholera, does not yet have the volume relationship with Indian fabless companies that would unlock discount pricing. Second, PSMC has no contractual obligation to load Tata's Indian fab, so its incentives point at its own existing customer base. The same arithmetic applies at the foundry level globally. TSMC, when approached by Orvis Semi for imaging fabrication, declined to provide engineering support. Sarkar tells Swarajya: "According to them, less volume doesn't make economic sense. They think, 'Oh you will come up with one chip a year that will be taken at roughly 100 to 200 thousand dollars. That means nothing to me in my economics. So I don't want to waste my time with this.'" Tower, an Israeli foundry, offered service to Orvis Semi but at more than the standard price. "Tower tells me, I will fabricate, but I am costlier. So, you have to pay me higher prices to fabricate the silicon. Now, we have to bear all this because we do not have a commercial fab. Now, if we had a commercial fab, probably all these problems would not have come," says Sarkar. This is the structural condition of being a sub-scale Indian fabless company today: foundries charge a premium because the volume is small. The packaging gap, mirrored The packaging layer mirrors this exactly. Over the past three months, Vervesemi has approached three Indian OSAT companies, that is, Kaynes Semicon (Sanand), Sahasra Semiconductors (Bhiwadi) and Suchi Semi (Surat), for specific package formats it needed for its chips. Kaynes responded that it did not have the required tooling, but could develop it, in over six months, and the quoted price was three times what Vervesemi was already getting from its foreign service partners, which was itself already twice the rate available to bigger players because of low volume. They did not receive a positive response from the other two. Indian OSATs are in the early phase of their life cycles. They have received substantial capital subsidies, typically 50 per cent from the centre and another 25 per cent from the state. But their tooling roadmaps and package portfolios are calibrated to the foreign customers who can guarantee volume. Kaynes Semicon, for instance, has tied up nearly all of its initial 4.6-billion-chips-per-annum capacity with Infineon, Alpha & Omega Semiconductor, and other global names. The OSATs need volume to justify their capital expenditure now; Indian fabless companies cannot supply that volume; so the OSATs book foreign customers and become, in effect, export-oriented contract packagers.

India's packaging layer is operational, world-class, and almost entirely booked by foreign clients. The loop that locked Indian designers out was never broken.

Singh's verdict is unsparing: "Indian packaging houses are not price competitive by three to five times. It is not ten or fifteen per cent." The same point is made about wafer pricing: in both cases the gap is one of multiples rather than percentage points. The regulatory tail that nobody is talking about The cost gap has a regulatory tail that public coverage has barely surfaced. When a fabless company ships a wafer abroad for fabrication and the packaged chips come back, the Indian customs system has trouble accepting the equivalence. What goes out is a thin wafer with hundreds of dies on it; what comes back is hundreds of packaged chips. To a customs officer, these are not the same goods. Each shipment generates a case-by-case review, and the Ministry of Electronics ends up writing intervention letters every time. Singh has filed seven such letters in recent months. Then there is the Reserve Bank of India's Bill of Entry rule. It requires that anything purchased abroad in dollars must be physically brought into India within two to three years. If goods are not physically brought in after a foreign exchange remittance has been made, the importer is required to repatriate the funds back to India. In plain language: if you send dollars out of India to buy goods for your business, but those goods never actually arrive in India, you cannot leave that money sitting abroad. You must bring that exact amount of money back into your Indian bank account. The photolithographic mask, however, bought from a Taiwan foundry in dollars, has a fifteen-year useful life and cannot be brought to India because it lives inside the foreign fab's cleanroom. It has no role anywhere else. Vervesemi has outstanding Bills of Entry that the RBI is questioning. MeitY has acknowledged the problem and asked the company to file a formal letter so the rule can be reviewed. This is the kind of friction that becomes lethal at scale. If India has 24 fabless companies today and the system requires case-by-case intervention for each shipment, what happens when there are 240, or 2,400? The volume problem India's 24 DLI companies, even on optimistic assumptions, will generate a combined volume of about 100 million chips per year. The operating cost of a single semiconductor fab is roughly $400 to $500 million per annum. To approach break-even purely on internal demand, a fab requires production volumes worth $4 to $5 billion. The mathematics, as Sarkar lays them out, is uncompromising: "Where is that volume going to come, unless you have 40,000 or four lakh fabless startup companies? Forty is too small. It is nothing. And out of 40, it will be 50-50, meaning 50 per cent of them will fail, which is normal," he tells Swarajya. Sarkar's structural proposal is bottom-up: a hundred supported companies per state; an academic silicon-access programme equivalent to what TSMC offers Taiwan's universities; a Production-Linked Incentive arrangement negotiated with TSMC, UMC and Tower for preferential pricing on Indian fabless designs while domestic foundries scale up; and an iDEX-style standing review-and-funding mechanism that commits to successful companies over a ten-to-fifteen-year horizon rather than asking them to re-apply every committee cycle. Two answers to the demand question There are, in essence, two ways the volume question can be answered, one looking outward and the other inward. The foreign-demand answer is plausible and has analytical force. Sinha's view is that legacy nodes are the right strategic bet because China is entering the legacy space and compressing margins, and Western customers will not buy Chinese chips. He explains to Swarajya: "Where China enters, the cost of manufacturing reduces, and margins reduce. People do not want to take chips from China. They are looking for an alternative. In their own country they will never be able to meet the price of China. So they are also looking for a trusted player in a different geographical location." India, in this theory, becomes the China-alternative for trusted legacy chips by the end of this decade. Tata Dholera is the proof-of-concept; once its lines stabilise and India shows that yields and quality are world-class, more fabs will follow. Sinha is candid that tier-one global foundry companies plan their construction five or six years in advance, and that the scheme only started in 2022. Two years were lost to scepticism alone. India is now on their radar. The Indian-demand answer is harder. It requires that the missing middle of the industry, what semiconductor analysts call product companies, gets built. A product company is the layer between an OEM and a chip designer. Maruti does not design the infotainment system in its cars. An infotainment-system company does, and that company designs or specifies the chips inside the system. Today, almost all of India's automotive and industrial infotainment systems are imported, complete with their chips, from Korean, Japanese and German product companies. Sinha himself acknowledges this layer is missing. "We only have to see the middle level, designing. Somebody should design on behalf of OEMs, and OEMs will give them requirements. There is a little gap, which we are trying to address in coming time," he tells Swarajya. Without Indian product companies, Indian fabless designs cannot easily reach Indian OEMs even if both exist.

India has the chip designers at the bottom and the OEMs at the top. The layer that connects them — the product company — is simply not there.