By vertically stacking layers of silicon circuits, chipmakers can dramatically increase computing density and speed while reducing energy use, offering a promising route to extend Moore’s law without shrinking transistors any further.
With vertical integration, you can distribute them across multiple layers.
“Vertical integration is already starting to make its way into commercial devices, particularly in specialized AI hardware, but monolithic integration is what unlocks the full promise of 3D chips,” Cao said.
The work was conducted within Illinois Grainger Engineering’s Center for Advanced Semiconductor Chips with Accelerated Performance, which counts IBM, Intel, and the Taiwan Semiconductor Manufacturing Company, among its industry partners.
Instead of stacking complete wafers, each device layer is sequentially built directly on top of the previous one during fabrication.
Newswise — For more than half a century, the power of computers has grown by shrinking transistors and packing them more tightly onto flat chips. It worked too well. Devices are now becoming so small that they start to be fundamentally limited by atomic dimensions and quantum effects.
The next leap can come from adding a new dimension: building upward. By vertically stacking layers of silicon circuits, chipmakers can dramatically increase computing density and speed while reducing energy use, offering a promising route to extend Moore’s law without shrinking transistors any further.
Illinois Grainger Engineering materials science and engineering professor Qing Cao explains, “Take something as simple as static random-access memory, which is universal in CPUs and GPUs. Today it takes six microelectronic devices called transistors on a single plane to store one bit of information. With vertical integration, you can distribute them across multiple layers. It’s like replacing a sprawling suburb with high-rises: you get the same functionality, but the spatial footprint is reduced while making communication between layers faster and more efficient.”
The most efficient approach, known as monolithic three-dimensional integration, builds each layer directly on top of the previous one to maximize interlayer connectivity. However, achieving this has been a longstanding technical challenge. Preparing high-quality silicon and fabricating high-performance devices normally require processes operating at 1,000 degrees Celsius, hot enough to destroy the metal wiring. For upper layers beyond the first, the temperature constraint, or “thermal budget,” is strictly set to 400 degrees.
A team of Illinois Grainger Engineering researchers led by Cao has now shown that it is possible to stay within that limit while still achieving high device performance across multiple tiers. Their newly invented process uses single-crystalline silicon — the main semiconductor used in industry — and has demonstrated device yields of 98‒100%, even in an academic laboratory cleanroom setting, indicating strong potential for industrial adoption.
“Vertical integration is already starting to make its way into commercial devices, particularly in specialized AI hardware, but monolithic integration is what unlocks the full promise of 3D chips,” Cao said. “For the first time, we have met the thermal budget of monolithic 3D integration using standard single-crystalline silicon and delivered unprecedented performance.”
This study appears in Nature as one of the journal’s rare research articles focused on silicon microelectronics.
The work was conducted within Illinois Grainger Engineering’s Center for Advanced Semiconductor Chips with Accelerated Performance, which counts IBM, Intel, and the Taiwan Semiconductor Manufacturing Company, among its industry partners. The team is now preparing to translate their process to an industrial semiconductor foundry.
Building circuits in three dimensions
Microelectronics manufacturing has been driven for the past 60 years by Moore’s law, which states that the density of transistors on a chip should double every two years. The electronics industry has adopted this principle as a production goal to increase the power and efficiency of computer processors. It has proven successful and steady for decades, but there are signs that the trend is starting to stall.
“In a sense, we’re hitting a limit imposed by physics,” Cao said. “If you look at the actual size of transistors, they’re not getting smaller, especially in terms of their contacted gate pitch. This is because we’re becoming limited by the intrinsic material properties of silicon and the fundamental rules of quantum mechanics. If we’re going to keep up the trend of increasing processing power of our microprocessors, we have to start thinking beyond just squeezing more devices on a single surface.”
Many experts believe that the way forward will be building upward to vertically integrate devices. It gives room for expansion without further shrinking individual devices. It also shortens the needed length of wiring, reducing parasitic capacitance while dramatically increasing the communication bandwidth between devices and circuit blocks. These features offer a crucial advantage for artificial intelligence and other forms of data-intensive computing.
The promise of monolithic integration
Current commercial three-dimensional chips are made by fabricating semiconductor devices on separate wafer substrates first and then bonding those wafers or dies together. While this approach has enabled successful products such as high-bandwidth memory and 3D V-Cache chips, it comes with substantial limitations. The alignment between layers is necessarily coarse, and the micron-scale vertical connections between layers called through-silicon via or TSV are relatively large and sparse.
In contrast, monolithic three-dimensional integration takes a fundamentally different approach. Instead of stacking complete wafers, each device layer is sequentially built directly on top of the previous one during fabrication. This procedure allows for much (10-100 times) denser interlayer vertical connections, smaller separations between layers, and precise interlayer alignment with nanometer-scale accuracy.
